ATMEGA8HVA-4CKU【PDF 117/196 页】MCU AVR 8K FLASH 4MHZ 36-LGA

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8024A–AVR–04/08

ATmega8HVA/16HVA

9.7

Watchdog Timer, Battery Protection and Coulomb Counter ADC Clock

The clock source for the Watchdog Timer, Battery Protection and Coulomb Counter ADC (CC-

ADC) is the Ultra Low Power RC Oscillator. The Oscillator is automatically enabled in all opera-

tional modes. It is also enabled during reset.

9.8

Clock Startup Sequence

When the CPU wakes up from Power-save, the CPU clock source is used to time the start-up,

ensuring a stable clock before instruction execution starts. When the CPU starts from reset,

there is an additional delay allowing the voltage regulator to reach a stable level before com-

mencing normal operation. The Ultra Low Power RC Oscillator is used for timing this real-time

part of the start-up time. Start-up times are determined by the SUT Fuses as shown in Table 9-1

on page 25. The number of Ultra Low Power RC Oscillator cycles used for each time-out is

shown in Table 9-2.

Note:

1. The actual value depends on the actual clock period of the Ultra Low Power RC Oscillator,

refer to ”Ultra Low Power RC Oscillator” on page 26 for details.

9.9

Clock Output

The CPU clock divided by 2 can be output to the PB0 pin. The CPU can enable the clock output

function by setting the CKOE bit in the MCU Control Register. The clock will not run in any sleep

modes.

9.10

System Clock Prescaler

The ATmega8HVA/16HVA has a System Clock Prescaler, used to prescale the Calibrated Fast

RC Oscillator. The system clock can be divided by setting the ”CLKPR – Clock Prescale Regis-

ter” on page 31, and this enables the user to decrease or increase the system clock frequency

as the requirement for power consumption and processing power changes. This system clock

will affect the clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkCPU and clk-

FLASH are divided by a factor as shown in Table 9-3 on page 32.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than

neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-

sponding to the new setting.

Table 9-2.

Number of Ultra Low Power RC Oscillator Cycles

Typ Time-out(1)

Number of Cycles

4 ms

512

8 ms

16 ms

32 ms

64 ms

128 ms

16K

256 ms

32K

512 ms

64K

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